Each multivibrator of the LS221 features a negative-transition-triggered input and positive-transition-triggered input either of which can be used as an inhibit input.

Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt/second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Following is function table for each monostable multivibrator:
74LS221 Function Table

Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length.

Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 100 kΩ). Pulse width is defined by the relationship: tw(out) = Cext*Rext*ln(2.0) ≈ 0.7 Cext*Rext; where tW is in ns if Cext is in pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25C temperature.

Once in the pulse trigger mode, the output pulse width is determined by tW = Rext*Cext*ln(2), as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than 0.5% from device to device.

If the duty cycle, defined as being 100*tW/T where T is the input period of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible (jitter is independent of Cext). With Rext = 100KΩ, jitter is not appreciable until the duty cycle approaches 90%.

Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. This is not the case for the LS221. Also note that it is recommended to externally ground the LS123 Cext pin. However, this cannot be done on the LS221.

The 74LS221 is a dual, monolithic, non-retriggerable, high-stability one shot. The output pulse width, tW can be varied over 9 decades of timing by proper selection of the external timing components, Rext and Cext.

Pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. Although all three inputs have this Schmitt-trigger effect, only the B input should be used for very long transition triggers (=1.0 µV/s). High immunity to VCC noise (typically 1.5 V) is achieved by internal latching circuitry. However, standard VCC bypassing is strongly recommended.

There are four basic modes of operation:
  • Clear Mode
    If the clear input is held low, irregardless of the previous output state and other input states, the Q output is always low.
  • Inhibit Mode
    If either the A input is high or the B input is low, once the Q output goes low, it cannot be retriggered by other inputs.
  • Pulse Trigger Mode
    A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above; Q will go low for a corresponding length of time.
    The Clear input may also be used to trigger an output pulse, but special logic preconditioning on the A or B inputs must be done as follows:
    • Following any output triggering action using the A or B inputs, the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse.
    • If the Clear pin is routinely being used to trigger the output pulse, the A or B inputs must be toggled as described above before and between each Clear trigger event.
    Once triggered, as long as the output remains high, all input transitions (except overriding Clear) are ignored.
  • Overriding Clear Mode
    If the Q output is high, it may be forced low by bringing the clear input low.

Typical power disippation for 74LS221 is 23 mW with maximum output pulse length 70s. This IC is packaged in 16-lead plastic DIP (Dual In-line Package), case 648-08.