74LS393 is dual version of the popular 74LS93 binary counter packed into single chip. Each clockhas their own individual clock and direct clear pin. Dual 4-bit versions can significantly improve system densities by reducing counter package count by 50%. Typical maximum count frequency 35 MHz. 74LS393 features buffered outputs reduce possibility of collector commutation.

Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The 74LS393 comprises two independent four-bit binary counters each having a clear and a clock input.

N-bit binary counters can be implemented with each package providing the capability of divide-by-256. This integrated circuit has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals.

Following is function table of counter sequence for each counter:

CountOutputs
QDQCQBQA
0LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5LHLH
6LHHL
7LHHH
8HLLL
9HLLH
10HLHL
11HLHH
12HHLL
13HHLH
14HHHL
15HHHH